Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...

This paper describes the process and tools used in the verification of a family of Secure Digital (SD) IP cores. The verification process described included SystemC verification, RTL simulation and ...

Today, memory “blocks” occupy an increasing portion of system-on-chip (SoC) designs. To achieve maximum density, the memory storage cell often incorporates leading-edge physical design rules that ...

Amongst various pre-silicon solutions, Software Simulation Platforms have always been the preferred environment due to early availability, ease of use, ease of access, lower cost as compared to FPGAs ...

At its Synopsys Converge event currently underway in Santa Clara, the company announced an array of tools and initiatives to ...

Three methods for testing functional equivalence are currently available to designers — conventional simulation, cone-based equivalence checking, and symbolic simulation. Most designers are familiar ...

Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power ...

Toshiba Electronic Devices & Storage Corporation ("Toshiba") has developed a model-based development (MBD) simulation technology that shortens verification times for automotive semiconductors by about ...

Many electronic design automation (EDA) solutions have evolved, which is not a bad thing. Evolution attempts to preserve the tools that are already in place—investments made by designers in languages, ...